Peter Bishop

First Published in 1988 by Ellis Horwood Limited

HTML Published in 1998

© Copyright Paul Naish and Peter Bishop 1988

Preface to printed edition

Preface to HTML edition

0 Introduction: From Discrete Logic Elements to Asics

0.1 What is an Asic?

0.2 The Role of Asics within Electronic Systems

0.3 Types of Asic

0.4 CAD Systems for Asic Design

0.5 Hierarchical Design

0.6 Asic Design Methodologies

0.7 Benefits of Asics

0.8 Conclusion

1.1 MOS Transistor Operation

1.2 CMOS Implementation of Primitive Parts

1.3 NAND, NOR and ANDNOR Gates

1.4 Decoder, Comparator and Inequality Detector

1.4.1 Decoder

1.4.2 Comparator

1.4.3 Inequality Detector

1.4.4 Multiplexer

1.4.5 Data Conditioning Elements

1.5 Transmission Gate and Tristate Buffer

1.6 Edge-sensitive Flip-flop

1.7 Classification of Signals

1.8 Classification of Base Primitives

1.9 The Asic Fabrication Process

1.10 Conclusion

2.1 Drive Capability, Absolute Fanout and Relative Fanout

2.2 Circuit Delay

2.3 Fanin Considerations in Choice of Gates

2.4 Slow Edges

2.5 Clock Buffering

2.5.1 Geometric Buffering

2.5.2 Tree Buffering

2.6 Transmission Gate

2.6.1 Constraints due to Bilateral Nature of Transmission Gate

2.6.2 Evolution of Tristate Buffer

2.7 Using Tristate Buffers in Bus Control

2.7.1 Use of Decoders for Bus Talker Selection

2.7.2 Lowering Bus Loading

2.8 Power Supply Considerations

2.9 Conclusion

3.1 Frequency Multiplier

3.2 Delay Line

3.3 Monostable

3.4 On-chip Oscillator

3.5 RS Flip-flop

3.6 JK Flip-flop

3.7 Implicit Flip-flop

3.8 Misuse of Control Elements

3.9 Output of One Latch feeding Clock of Another

3.10 Gated Clock

3.11 Negative Clock Edge

3.12 Asynchronous Clear - Short Reset Pulse

3.13 Asynchronous Clear - Long Reset Pulse

3.14 Central Clock Generator

3.15 Conclusion

4.1 Definition of Synchronicity

4.2 Primitive Synchronous Parts

4.3 Synchronously Cleared D-type Flip-flop

4.4 E-type Flip-flop

4.5 T-type Flip-flop

4.6 Synchronous RS Flip-flop

4.7 R-type Flip-flop

4.8 State Generation

4.8.1 Unconditional Execution of States

4.8.2 Conditional Execution of States

4.9 Central Enable Generator

4.10 Synchronous Clear

4.11 Eliminating Clock Skew

4.12 Conclusion

5.1 Mutually Synchronous Systems

5.2 Synchronous Systems which are Mutually Asynchronous

5.3 Asynchronous Inputs to Synchronous Systems

5.4 Polling and Handshakes based Only on Edge-sensitive Elements

5.5 Security of Transmitted Data in Handshakes

5.6 Asics in Microprocessor Memory Maps

5.7 Meta-stability

5.8 Conclusion

6.1 Uses of RAM

6.2 Level-sensitive Latch

6.3 Register File

6.4 Static RAM

6.5 Dynamic RAM

6.5.1 Reading from DRAM

6.5.2 Writing to DRAM

6.5.3 Timing of DRAM Access

6.5.4 Refreshing DRAM

6.6 Conclusion

7.1 Ring Buffer

7.1.1 Substreaming and Superstreaming

7.1.2 Ring Buffer Layout

7.2 Linear Transforms and Cross-interleaved Codes

7.3 FIFO

7.4 General Resource Access - Gentleman's Agreement

7.5 Conclusion

8.1 Pipelining and Serial Processing

8.1.1 Pipelining

8.1.2 Serial Systems

8.2 Partitioning a System

8.2.1 Every Last Inverter?

8.2.2 Repeated Structures

8.2.3 Asics and Programmable Logic

8.2.4 Highly Asynchronous Systems

8.3 Conclusion

9.1 Commercial Considerations in Test Strategies

9.1.1 Consequences of Failure

9.1.2 Factors in Determining Test Strategy

9.2 Concepts of Testing

9.2.1 Known Good Circuit

9.2.2 Test Equipment

9.2.3 Initialisation

9.2.4 'Stuck-at' Faults

9.2.5 Controllability and Observability

9.2.6 Effect of Controllability on Observability

9.3 Methods of Test

9.3.1 Post-design

9.3.2 Ad-hoc

9.3.3 Scan Path

9.3.4 PRBS Generator and Signature Analyser

9.3.5 Hybrid Techniques

9.3.6 Exploiting Buses

9.3.7 Testing RAM

9.4 Hierarchy of Control

9.5 Tools for Test Vector Development

9.5.1 Nodal Activity Check

9.5.2 Testability Analyser

9.5.3 Test Vector Grading

9.5.4 Automatic Test Vector Generation

9.6 Conclusion

10.1 Advantages and Disadvantages of Register Transfer Models

10.2 Languages for Register Transfer Models

10.3 Register Transfer Models in Pascal

10.3.1 Data Structure

10.3.2 Program Structure

10.3.3 Example - Pascal Accumulator Model

10.4 Register Transfer Models in HDL

10.4.1 Example - HDL Accumulator Model

10.5 Conclusion

11.1 Synchronous, Hierarchical Design

11.2 Asynchronous Elements

11.3 Design for Production

11.4 Postscript